1. Field of the Invention
The present invention relates to semiconductor memory apparatuses and systems, and related methods of performing read operations. More particularly, the invention relates to stacked semiconductor memory apparatus and systems, and related methods of performing read operations using a compound read buffer.
2. Description of the Related Art
The emergence of mobile consumer electronics, such as cellular telephones, laptop computers, Personal Digital Assistants (PDAs), and MP3 players to name but a few, has increased the demand for compact, high performance memory devices. In many ways, the modern development of semiconductor memory devices may be viewed as a process of providing the greatest number of data bits at defined operating speeds using the smallest possible device. In this context, the term “smallest” generally denotes a minimum area occupied by the memory device in a “lateral” X/Y plane, such as a plane define by the primary surfaces of a printed circuit board or module board.
Not surprisingly, restrictions of the tolerable lateral area occupied by a memory device have motivated memory device designers to vertically integrate the data storage capacity of their devices. Thus, for many years now, multiple memory devices that might have been laid out adjacent to one another in a lateral plane have instead been vertically stacked one on top of the other in a Z plane relative to the lateral X/Y plane.
Recent developments in the fabrication of so-called “Through Silicon Vias (TSVs)” have facilitated the trend towards vertically stacked semiconductor memory devices. TSVs are vertical connection elements that pass substantially, if not completely, through a substrate and are fully contained within the periphery of the stacked substrates. TSVs are distinct from and have largely replaced vertical connection elements running up the outer edges of stacked memory devices. Such external wiring (i.e., wiring disposed on the periphery) was conventionally required to operatively connect the stacked devices. But this wiring increases the overall lateral area occupied by the stacked device and typically requires interposing layers between adjacent substrates in the stack. Because TSVs pass vertically upward through a substrate, no additional lateral area is required beyond that defined by the periphery of the largest substrate in the stack. Further, TSVs tend to shorten the overall length of certain critical signal paths through the stack of devices, thereby facilitating faster operating speeds.
Stacked semiconductor memory devices are one type of three dimensional (3D) integrated circuits. That is, from the standpoint of other system components such as a memory controller, a 3D memory apparatus functions as an integral memory device. Data write and data read operations are processed by the 3D memory device in order to store write data or retrieve read data in ways generally applicable to non-stacked (i.e., single substrate) memory devices. Yet, the 3D memory apparatus is able to store and provide a great deal more data per unit lateral surface area, as compared with a non-stacked memory device.
Thus, through the use of TSVs or similar stack fabrication processes, memory apparatuses implemented with a plurality of vertically stacked memory devices are able to store and provide a large amount of data using a single integrated circuit having a relatively small lateral surface area footprint. However, surface area efficient storage and retrieval of data from a 3D memory apparatus poses a number of related challenges to the memory apparatus and system designer.
Consider for the moment the conventional single layer Dynamic Random Access Memory (DRAM) 8 shown in Figure (FIG.) 1. A DRAM memory core 10 comprises a great number of individual memory cells arranged in relation to a matrix of row and column signal lines. Each memory cell is able to store write data in response to a write command and provide read data in response to a read command received from an external device (not shown), such as a memory controller or processor. Read/write commands result in the generation of certain control signals (e.g., a row address, a column address, enable signals, etc.) which along with certain control voltages are applied to memory core 10 through related peripheral devices, such as row decoder 12 and column decoder 11.
During a write operation, write data (i.e., data intended to be stored in memory core 10) passes from the external circuit (e.g., an external memory, an external input device, a processor, a memory controller, a memory switch, etc.) to a write buffer 14 through a write control circuit 15. Once stored in write buffer 14, the write data may be written to memory core 10 through conventional functionality associated with an Input/Output (I/O) driver 13 which may include, for example, sense amplifier and page buffer circuitry.
During a read operation, applied control voltages, as well as the control signal outputs of row decoder 12 and column decoder 11 generally cooperate to identify and select one or more memory cell(s) in memory core 10 and facilitate the provision of signals indicating the value of data stored in the memory cell(s). The resulting “read data” typically passes through I/O driver 13 to be stored in a read buffer 16. Read data stored in read buffer 16 may be subsequently provided to the external circuit under the control of read control circuit 17.
In the foregoing example, write buffer 14 and read buffer 16 are generally used to harmonize the timing characteristics associated with the data access and transfer functionality within DRAM 8 with different timing characteristics associated with the external circuit (i.e., synchronous input/output requirements defined by an external clock signal). Stated in other terms, write buffer 14 and read buffer 16 are used to respectively to control the write data and read data latencies for DRAM 8 in relation to the requirements of the external circuit.